wikiOptimization of AMD EPYC 9004 Genoa and Bergamo working memory performance
Processors of the AMD EPYC 9004 Genoa and Bergamo series have over twelve Memory Controller, which can each control a memory channel. Up to two DIMMs are possible per channel. To achieve an optimal total performance, it is useful to ensure a balanced allocation. In this article, we show DIMM configurations that are frequently used.
Basics
Processors of AMD EPYC 9004 series
- 12 memory controller per CPU
- 1 memory channel per Memory Controller
- 2 DIMMs per channel (maximum 24 DIMMs per CPU = 48 DIMMs in a Dual-CPU system)
Configurations
The following tables show ideal allocations of different RAM slots.
Important hint for maximum storage bandwidth: The tables show measurements of a bandwidth test with STREAM Triad.[1] The highest possible memory bandwidth is particularly relevant in the HPC environment. In other application areas, the influence of the storage bandwidth on the total performance is lower and is dependent on the respective application. Tests with SPECint_rate_base2006, for example, show that the SPEC-Benchmark reaches up to 90 per cent performance only with a storage bandwidth of 35 per cent.[2] RAM allocations with less modules, however, lower the maximum reachable storage bandwidth, but need less energy and offer a good expandability for the future.
Single-CPU systems with 12 DIMM slots
The following table shows possible DIMM configurations of a Single-CPU system with a mainboard with 12 DIMM slots (for example Supermicro H13SSL-NT):
| module size | 2 DIMMs | 4 DIMMs | 6 DIMMs | 8 DIMMs | 10 DIMMs | 12 DIMMs |
|---|---|---|---|---|---|---|
| 16 GB | 32 GB | 64 GB | 96 GB | 128 GB | 160 GB | 192 GB |
| 32 GB | 64 GB | 128 GB | 192 GB | 256 GB | 320 GB | 384 GB |
| 64 GB | 128 GB | 256 GB | 284 GB | 512 GB | 640 GB | 768 GB |
| 96 GB | 192 GB | 384 GB | 576 GB | 768 GB | 960 GB | 1.152 GB |
| Maximum storage
bandwidth [3] |
~18% | ~35% | ~51% | ~68% | ~84% | ~100% |
More information
- How to Populate AMD EPYC 9004 Genoa Memory Channels (www.servethehome.com, 11.11.2022)
- DDR5 Memory Channel Scaling Performance With AMD EPYC 9004 Series (www.phoronix.com, 06.01.2023)
References
- ↑ STREAM: Sustainable Memory Bandwidth in High Performance Computers (www.cs.virginia.edu)
- ↑ Memory Performance of Xeon scalable processor (Skylake-SP) based Systems (sp.ts.fujitsu.com)
- ↑ Balanced Memory Configurations with 4th Generation AMD EPYC Processors (lenovopress.com)
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Author: Werner Fischer Werner Fischer, working in the Knowledge Transfer team at Thomas-Krenn, completed his studies of Computer and Media Security at FH Hagenberg in Austria. He is a regular speaker at many conferences like LinuxTag, OSMC, OSDC, LinuxCon, and author for various IT magazines. In his spare time he enjoys playing the piano and training for a good result at the annual Linz marathon relay.
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Translator: Alina Ranzinger Alina has been working at Thomas-Krenn.AG since 2024. After her training as multilingual business assistant, she got her job as assistant of the Product Management and is responsible for the translation of texts and for the organisation of the department.
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