wikiAMD Genoa(-X) and Bergamo
Genoa(-X) and Bergamo are code names for processors of the AMD EPYC 9004 series. They present the fourth generation of processors with the so-called zen-microarchitecture and are, therefore, the successor of processors from the Milan series. The new series uses the new SP5 base and is manufactured in 5nm.
In the following, the innovations and technical details of the new processor line are explained.
Structure
AMD processors of the Zen 4 architecture rely on the familiar, in Core Complex the (CCD) organized, chiplets.
Up to 12 Chiplets are possible per CPU. Every chiplet contains:
- 8 cores
- 1 MB L2-Cache per core
- Shared 32 MB L3-Cache
All chiplets are connected with the so-called I/O-Die. In addition to the central interface for all chiplets, the I/O-Die provides following technologies:
- 12 Memory controller
- PCIe Gen 5 controller
- Infinity fabric controller
- SATA controller
- Compute Express Link (CXL) controller
Furthermore, it uses the AMD Secure Processor technology.
Innovations
The AMD EPYC 9004 series processors offer innovations in manufacturing, interface support, and instruction sets.
Processors of the Genoa and Bergamo series are manufactured in 5nm. This results in a higher base clock speed.
It supports PCI-Express in the 5th generation and increases the bandwidth for the connection of data storage on 32 GT/s per lane. In total, up to 128 lanes can be used for a single socket configuration and up to 160 lanes for a dual socket configuration.
The series also makes the leap to DDR5 RAM. 12 channels are provided via memory controller.
There are also innovations in the command set area. With Genoa and Bergamo, VNNI and BFLOAT16 are also supported.
Milan and Genoa comparison
The following chart shows the improvements of the Zen 4 architecture based on Genoa and Bergamo processor series compared to the Zen 3 AMD processors with code name Milan. For an overview comparing the current processor series with each other, see also AMD EPYC 9004 Genoa and Bergamo.
| Zen 3 | Zen 4 | explanation | |
|---|---|---|---|
| LDQ | 72 | 88 | Load Queue of Load/Store Unit (LSU)[1] |
| STQ | 64 | 64 | Store Queue of LSU[2] |
| Micro-op cache | 4k ops | 6.75k ops | SRAM Puffer[3] |
| L1 I/D-cache | 32/32k | 32/32k | Layer 1 Instruction/Data-Cache[4] |
| L2 cache | 512k | 1M | Layer 2 Cache |
| L3 cache/core | 4M | 4M | Layer 3 Cache per core |
| L2 TLB | 2k | 3k | Layer 2 Translation Lookaside buffer[5] |
| L2 latency | 12 cycles | 14 cycles | Layer 2 Latenz |
| L3 latency | 46 cycles | 50 cycles | Layer 3 Latenz |
| Issue width (Int + FP/SIMD) | 10+6 | 10+6 | Anzahl der Instruktionen per Taktzyklus (Integer + Floating Point / Simple Instruction Multiple Data)[6][7] |
| Int reg | 192 | 224 | Integer registration |
| Int scheduler | 96 | 96 | Integer Scheduler |
| FP reg | 160 | 192 | Floating Point registration |
| ROB | 256 | 320 | re-order buffer[8] |
| FADD/FMUL/FMA latency | 3/3/4 cycles | 3/3/4 cycles | Floating Point Addition / Floating Point Mulitplier / Fused Multiply-Add Latenz |
| L1 BTB | 2x 1k | 2x 1.5k | Layer 1 Branch Target Buffer[9] |
| L2 BTB | 2x 6.5k | 2x 7k | Layer 2 Branch Target Buffer |
More information
- AMD EPYC of the 4th generation: Performance and energy efficiency (TKmag Webinar recording, 24.08.2023)
- AMD EPYC Genoa Gaps Intel Xeon in Stunning Fashion (www.servethehome.com, 10.11.2022)
- AMD EPYC Bergamo is a Fantastically Fresh Take on Cloud Native Compute (www.servethehome.com, 19.07.2023)
References
- ↑ Load/Store Unit (LSU) (docs.boom-core.org, 05.10.2023)
- ↑ Load/Store Unit (LSU) (docs.boom-core.org, 05.10.2023)
- ↑ Static Random Access Memory (wikipedia.org, 05.10.2023)
- ↑ CPU Cache (wikipedia.org, 05.10.2023)
- ↑ Translation Lookaside Buffer (wikipedia.org, 05.10.2023)
- ↑ Wide Issue (wikipedia.org, 05.10.2023)
- ↑ Flynn's taxonomy (wikipedia.org, 05.10.2023)
- ↑ Re-Order Buffer (wikipedia.org, 05.10.2023)
- ↑ Branch Target Buffer (wikipedia.org, 05.10.2023)
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Author: Stefan Bohn Stefan Bohn has been employed at Thomas-Krenn.AG since 2020. Originally based in PreSales as a consultant for IT solutions, he moved to Product Management in 2022. There he dedicates himself to knowledge transfer and also drives the Thomas-Krenn Wiki.
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Translator: Alina Ranzinger Alina has been working at Thomas-Krenn.AG since 2024. After her training as multilingual business assistant, she got her job as assistant of the Product Management and is responsible for the translation of texts and for the organisation of the department.
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