PCIe Reference Clock
PCI Express supports multiple clock modes. This Wiki article shows an overview of the different modes.
Overview
The following clock modes are defined:[1][2][3]
- Common REFCLK Common Reference Clock
- Data Clocked (only PCIe 2.0 and 3.0)
- Independent REFCLK (formerly Separate) Reference Clocks
- Separate Reference Clocks with No SSC (SRNS)
- Separate Reference Clocks with Independent SSC[4] (SRIS)

| PCIe version | Common REFCLK
Rx Architecture (CC) |
Data Clocked
Rx Architecture |
Independent REFCLK
Architecture (IR) | |
|---|---|---|---|---|
| SRNS | SRIS | |||
| PCIe 1.0 | ✔ | - | ? | - |
| PCIe 2.0 | ✔[7][8] | ✔ | ||
| PCIe 3.0 | (x) | |||
| PCIe 4.0 | - | ✔ | ||
| PCIe 5.0 | ||||
| PCIe 6.0 | ||||
More information
- Videos about IDT:
- Videos about Microchip Technology:
- Clocking Architectures in PCI-Express (www.truechip.net, 19.07.2022)
- Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1 - Separate Reference Clock with Independent SSC (SRIS) (edc.intel.com) Inclusion of the reference clock in the cable requires an expensive shielding solution to meet EMI requirements. [...] The need for an inexpensive PCIe* cabling solution for PCIe* SSDs requires a cabling form factor that supports non-common clock mode with spread spectrum enabled, such that the reference clock does not need to be part of the signals delivered through the cable. This clock mode requires the components on both sides of a link to tolerate a much higher ppm tolerance of ~5600 ppm compared to the PCIe* Base Specification defined as 600 ppm.
References
- ↑ Clocking Architectures in PCI-Express (www.truechip.net, 19.07.2022)
- ↑ Verification of SRIS/SRNS Clocking - Whitepaper (PDF) (www.esaindia.com, 19.07.2022)
- ↑ Selecting the Optimum PCI Express Clock Source (PDF) (www.skyworksinc.com, 19.07.2022)
- ↑ Spread Spectrum Clocking (de.wikipedia.org)
- ↑ PCI Express 4.0 Electrical Previews - Page 5 (pcisig.com, 2014) PCIe 4.0 Overview [...] New features [...] Support for independent Refclk clocking mode with SSC (SRIS) (Bild)
- ↑ PCI Express 4.0 Electrical Previews - Page 20 (pcisig.com, 2014) IR with SSC (SRIS) defined in 3.0 ECN and 4.0 specification (Bild)
- ↑ congatec Application Note - PCI Express Reference Clock Design Considerations (www.congatec.com, 30.09.2020) The Data Clocked Rx architecture is only supported by PCIe 2.0 and 3.0 and is not supported by most chipsets. Therefore, the Data Clocked Rx architecture is usually not recommended.
- ↑ Why does PCIe 5.0 architecture not support an embedded clock? (www.asteralabs.com)
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Author: Werner Fischer Werner Fischer, working in the Knowledge Transfer team at Thomas-Krenn, completed his studies of Computer and Media Security at FH Hagenberg in Austria. He is a regular speaker at many conferences like LinuxTag, OSMC, OSDC, LinuxCon, and author for various IT magazines. In his spare time he enjoys playing the piano and training for a good result at the annual Linz marathon relay.
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Translator: Alina Ranzinger Alina has been working at Thomas-Krenn.AG since 2024. After her training as multilingual business assistant, she got her job as assistant of the Product Management and is responsible for the translation of texts and for the organisation of the department.
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