wikiNVMe basics
NVM Express (NVMe) is a SSD optimized interface (Register-Level-Interface) for the PCIe bus. The specification is not limited on SSDs, but generally designed for non-volatile (persistent) memory. The protocol was developed with attention for optimized command administration (submission and completion). Due to the high speed of PCIe SSDs, care was also taken to ensure that as many commands as possible could be processed in parallel. Important hint: Although the SSDs are connected via the PCIe bus, NVMe is used as the protocol.
Main features
The NVMe interface has the following key attributes:[1]
- simplified command set
10 admins and 3 I/O commands that are classified as "required".
- Queuing Model
Support for up to 64K I/O queues with 64K each in flight commands per queue. In addition, priorities can be assigned to the individual queues. For NVMe, you have to differ between Submission Queues and Completion Queues. Messages are sent from the host to the controller in the submission queues and the Completion Queue vice versa (for example to signalize the completion of I/O).These queues are quite efficient in Multi-CPU architectures, as there are assigned queues and interrupts per core.
- MSI-X Interrups
Allow more interrupts per device and more targeted interrupts in Multi-CPU environments.[2]
- multiple namespaces per device
A NVMe device can divided into different namespaces that form a logical unit.
- Multipath I/0
Dual Port SSDs or SSDs behind PCIe switches can get connected to several hosts. Unique IDs are generated for each namespace to distinguish between the hosts.
- autonomous power states
Power State changes are made by an OS without management
- lower latencies
The reduction in latency can be attributed to the more efficient execution of commands. Unlike AHCI, NVMe does not require registers to be read in order to issue commands. With NVMe, it is sufficient to write the new values into the queues.[3]
Performance
The PCIe interface provides a high performance and is suitable for SSDs:
- ~1 GB/s per lane (Gen3), for example bei 8-fach PCIe 3.0 8GB/s per device
- latencies from 10us to 3 us
- direct connection to CPU (GEN3) and not via chipset (GEN2)
Linux history
Compare History of NVMe in Linux (intel.com):
- Kernel 3.3 2011, Merge in Mainline 2012 (NVMe 1.0c)[4]
- Kernel 3.6, Supports blocks greater than 512 byte
- Kernel 3.9, Discard/Trim
- Kernel 3.10, Bio Splitting
- Kernel 3.12, Power Management: Suspend/Resume
- Kernel 3.14, Controller Failure and Recovery
- Kernel 3.15, Hot Plug CPU
- Kernel 3.16, Flush
- Kernel 3.19, blk-mq Driver[5]
- Kernel 4.0, device-mapper multipath
- Kernel 4.1, Data integrity extensions
Form factors
M.2
The M.2 interface form factor is particularly common in the client sector.[6] The standard replaces the mSATA interface, as M.2 is more flexible in terms of use and interface diversity.[7]
U.2 2,5" (SFF-8639)
The U.2 interface was recently described as SFF-8639, the interface records NVMe SSDs in 2,5".U.2 is not yet widely used in client environments, but M.2 to U.2 adapters are available for conversion to U.2.[8] These adapters often convert to miniSAS HD connectors, which in turn terminate in U.2 connectors via cable. Another advantage of U.2 is that the connector is compatible with SATA, SAS, and SATA Express.[9]
Add-In (PCIe)
SSDs for PCIe-slots are the traditional way for NVMe SSDs as add-in card.[10][11] PCIe-SSDs used the same slot before the NVMe-specification, but did not provide a standardized interface.
References
- ↑ NVMe based PCIe SSD Validation Challenges and Solutions (snia.org)
- ↑ MSI-HOWTO.txt (lwn.net)
- ↑ A Comparison of NVMe and AHCI (sata-io.com)
- ↑ This driver is for devices that follow the NVM Express standard
- ↑ This converts the NVMe driver to a blk-mq request-based driver.
- ↑ 950 Pro review: Samsung’s first PCIe M.2 NVMe SSD (arstechnica.com)
- ↑ M.2 (wikipedia.org)
- ↑ ASRock Announces U.2 Kit For M.2 Slots and Front USB 3.1 Panel With Type-A and Type-C Ports(thessdreview.com)
- ↑ NVM ExpressTM Ecosystem Enabling PCIe NVMe Architectures (flashmemorysummit.com)
- ↑ PCI Express Based Storage: Crossing the Technology Adoption Chasm, IDF 2013 Folie 9-11
- ↑ Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express (slideshare.net)
Author: Georg Schönberger
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Translator: Alina Ranzinger Alina has been working at Thomas-Krenn.AG since 2024. After her training as multilingual business assistant, she got her job as assistant of the Product Management and is responsible for the translation of texts and for the organisation of the department.
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